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SM

SOBITHA M

Electronics and Communication Engineering student · VLSI ,Embedded Systems & Digital Design

Chennai, Tamil Nadu, India

@sobitha1

LinkedIn GitHub

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🎓 Bachelors of Engineering in Electronics and Communication Engineering at Velammal Engineering College · Graduating 2028

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About

Electronics and Communication Engineering student with hands-on experience in digital design, Verilog HDL, microcontrollers, and sensor-based projects. Interested in embedded systems, hardware development, and practical learning through technical projects.

Education

  • Bachelors of Engineering in Electronics and Communication Engineering
    Velammal Engineering College
    Electronics and Communication Engineering (ECE) · 2024 – 2028
  • Higher Secondary Education
    Velammal Vidhyashram
    PCM-CS · 2023 – 2024
  • Secondary Education
    Velammal Vidhyashram
    2021 – 2022

Skills

<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
C I2C UART Fsms ESP32 Python Debugging RTL Design Verilog Hdl Logic Design RTL Simulation Fault Detection System Validation Sensor Interfacing Digital Electronics Functional Verification Microcontroller Programming

Tools / apps / platforms

<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
Arduino Arduino IDE

Projects

  • IoT-Based Real-Time Small Industrial Disaster Detection System
    ESP32, sensors

    Developed an IoT-based monitoring system using ESP32 and sensors for detection of abnormal environmental conditions. Implemented real-time data acquisition, sensor validation, fault-detection logic, debugging, and functional testing to improve reliability.

  • Smart Building Energy Monitoring & Optimization System
    IoT

    Ongoing retrofit-friendly IoT energy monitoring and optimization system for commercial and residential buildings. Developing a non-invasive sensing architecture using current transformers and occupancy sensing.

  • RTL Digital Design using Verilog
    Verilog HDL

    Designed a 2:1 multiplexer, decoder, comparator, checker, and reset-enable register using Verilog HDL. Applied combinational and sequential RTL, clock and reset logic, and basic functional verification; simulated and debugged designs to validate expected functionality.

Courses & certifications

  • Technical Training · All India Radio (AIR)

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