SNEHAL HEMANT VIBHUTE

About

Electronics engineering student graduating in 2027 with experience in embedded systems, FPGA design, and IoT. Built production-ready systems with high uptime and improved FPGA resource efficiency through optimization.

Experience

• Electronics Design Intensive Training Program
  InternPe
  Jan 2026 – Feb 2026

  Completed intensive training covering RTL design fundamentals, Xilinx synthesis workflows, timing closure optimization, and formal verification techniques with hands-on FPGA implementations.

• VLSI DESIGN Internship
  Intershala
  Oct 2025 – Sep 2025

  Completed a VLSI Design internship through Internshala, gaining practical knowledge of digital design, CMOS logic, Verilog HDL, RTL design, simulation, and FPGA/ASIC concepts.

Education

• 2027 PV
  B.Tech

  Padmabhooshan Vasantraodada Patil Institute of Technology, Sangli

  Electronics Engineering · 2027

  Electronics Engineering

Skills

Tools / apps / platforms

Projects

• Smart door lock sysrem
  Embedded Systems, Arduino

  Designed a password-based smart door lock using Arduino, 4×4 keypad, LCD, servo motor, and buzzer. Implemented secure access control with password verification and automatic door locking/unlocking.

• CMOS Inverter Design and Characterization
  LTspice, Analog Circuit Design

  Designed and characterized a CMOS inverter circuit, achieving noise margins of 0.4V+ and measuring propagation delay and power consumption via LTspice simulations. Conducted DC and AC analysis, validating circuit performance against specifications and optimizing transistor sizing for improved efficiency.

• 4-Bit Ripple Carry Adder — FPGA Implementation
  Verilog, Xilinx Vivado, Artix-7 FPGA

  Designed and synthesized a 4-bit ripple carry adder in Verilog, achieving sub-2ns propagation delay and reducing FPGA resource utilization by 18%. Performed functional verification and static timing analysis on Xilinx Artix-7 FPGA, validating correctness across all test vectors with zero timing violations.