Shravani Lalasaheb Indalkar

About

Aspiring VLSI and Embedded Systems Engineer with hands-on exposure to Verilog HDL, FPGA design, and digital electronics. Interested in emerging technologies and solving real-world engineering challenges.

Experience

• Internship
  Mazagon Dock Shipbuilders Ltd.

  Explored production, electrical, electronics, and quality assurance departments; gained insight into naval ship construction, communication systems, and engineering practices.

• Intern
  ZTTC BSNL, Pune · Pune

  Completed vocational training and internship in networking; gained knowledge about 4G/5G networks and worked on antenna-related tasks.

• Intern
  The Agnirva Space

  Completed an 8-week space internship and gained fundamental insights into space science.

Education

• 2027
  BE

  SIES Graduate School Of Technology

  Electronics and Telecommunication Engineering (ETE) · Aug 2022 – 2027

  Electronics and Telecommunication Engineering (ETE) · Aug 2022 – 2027
• 2022 VB
  Higher Secondary

  Vidya Bhawan Junior College of Nerul

  Aug 2021 – Mar 2022

  Aug 2021 – Mar 2022
• 2020 VB
  High School

  Vidya Bhawan Higher Education School

  Feb 2019 – Apr 2020

  Feb 2019 – Apr 2020

Skills

Languages

Projects

• Toffee Vending Machine
  Verilog HDL, FPGA

  Developed an FPGA-driven toffee vending machine using FSM-based control for multi-coin input, automated dispensing, and accurate change computation.

• Flappy Bird Game using FPGA Board
  Verilog HDL, Xilinx ISE, VGA

  Designed and implemented a Flappy Bird game on a Spartan-6 FPGA using Verilog HDL and Xilinx ISE; developed VGA display controller, game logic, collision detection, and score tracking.

• FPGA Smart Sensor Hub using reusable IP cores of UART, SPI, I²C
  Verilog HDL, FPGA, UART, SPI, I²C

  Designing reusable UART, SPI, and I²C IP cores in Verilog HDL on a Spartan-6 FPGA for multi-protocol communication; developing an FPGA-based smart sensor hub for multi-sensor real-time data acquisition and processing.

Courses & certifications

• UVM · Udemy
• ASIC Verification · Udemy
• Antenna Design · SIES Graduate School of Technology
• Embedded System · NIELIT
• VSD - Physical Design · Udemy
• ASIC Design and Verification · Udemy
• Design Verification with SystemVerilog · Udemy

🏆 Achievements & awards

• District Level Drawing Competition Winner

  Won a district-level drawing competition presented for Swachh Sarvekshan Bharat.

⚽ Extracurricular activities

• App Developer Head, Technical Team, SIESGST

  Served as a technical coordinator, contributed to app development for the SIESGST Technical Team, and helped organize BYTECAMP, Navi Mumbai's largest hackathon.

• Dancer

  Experienced in semi-classical dancing and participated in various competitions.

🎯 Hobbies & interests

• Drawing
• Dancing