About
Electronics and Communication Engineering undergraduate specializing in CMOS analog/digital IC layout design, with hands-on internship experience at Mirafra Technologies. Proficient in Cadence Virtuoso and layout verification techniques, and seeking full-time VLSI physical design roles.
Experience
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Analog Layout Design InternMirafra TechnologiesFeb 2026 – Aug 2026
Designed and verified CMOS layouts for logic gates, half adder, full adder, D flip-flop, Op-Amp, LDO, and word line driver layouts. Performed DRC and LVS verification and applied matching and optimization techniques.
Education
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Bachelor of Engineering (B.E.)A J Institute of Engineering and TechnologyElectronics and Communication Engineering · 2022 – 2026
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Science StreamGovernment PU CollegeScience · 2020 – 2022
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Class XSGVP SchoolSSLC · 2019 – 2020
Skills
Tools / apps / platforms
Languages
Projects
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AI-Based Tear Fern Testing using CNNCNN
Built a CNN-based image classification pipeline to automate tear fern pattern grading for dry-eye diagnosis, improving consistency over manual interpretation. Recognized with First Prize at the college project exhibition.
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Smart Low-Level Laser Cap
Designed a wearable low-level laser therapy device for scalp health, engineering power regulation and safety cut-off circuits to ensure safe laser exposure levels. Delivered a functional prototype balancing safety, comfort, and everyday usability.
Courses & certifications
- PCB Designing using KiCad · Kakunje Software Pvt Ltd
- VLSI System on Chip Design Overview · Maven Silicon
- VLSI for Beginners · National Institute of Information and Technology
- Complete Verilog HDL Programming With Examples · Udemy
🏆 Achievements & awards
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First Prize in Project Exhibition · 2025
Awarded for the AI-Based Tear Fern Testing project.
🎯 Hobbies & interests
- Movies
- Cooking
- Music
- Reading Books