Sahana Patil

Electronics & Communication Engineering student · VLSI / FPGA / Python

Belagavi, Karnataka, India

@sahana_patil

0 followers

About

Electronics and Communication Engineering student with an interest in VLSI, FPGA design, and Python programming. Has hands-on academic exposure to digital electronics, Verilog HDL, RTL design basics, FPGA development using Vivado, and Python fundamentals.

Experience

VLSI and PYTHON intern

Company · Bengaluru and remote

Jan 2026 – Jul 2026

Learned the fundamentals of digital electronics, logic gates, Boolean algebra, and combinational and sequential circuits. Gained basic knowledge of Verilog HDL, RTL design, and simulation using relevant tools. Improved problem-solving, technical, teamwork, Python, and debugging skills.

Education

2026

Bachelor of Engineering (B.E.)

S G Balekundri Institute Of Technology

Electronics and Communication Engineering (ECE) · 2022 – 2026

Electronics and Communication Engineering (ECE) · 2022 – 2026

Skills

6 to 12 months

Python Debugging RTL Design Verilog Hdl Digital Design

<3 months

VLSI FPGA Databases Simulation File Management Exception Handling

Tools / apps / platforms

<3 months

Microsoft Excel Visual Studio Code

Languages

Fluent

Hindi Speak English Speak Kannada Speak

Projects

Design and Verification of I²C Communication Protocol Using Verilog HDL

Verilog HDL, Vivado

Designed and simulated serial communication between master and slave devices using I²C protocol concepts including START/STOP conditions, slave addressing, data transmission, and acknowledgment signals.
Student Management System Using Python

Python, Visual Studio Code

Beginner-friendly project to manage student information, add student details, and view stored records. Used Python concepts such as variables, lists, dictionaries, functions, loops, and conditional statements.

Courses & certifications

PCB design workshop

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