Roshan surwase

About

3rd-year B.Tech Semiconductor Engineering student with hands-on exposure to VLSI Physical Design, ASIC flow, and RTL design. Completed Synopsys internship/training and workshop experience with practical work in ICC2, Design Compiler, Verilog, VCS, Verdi, Linux, and TCL.

Experience

• Physical Design Head
  DYPIU
  Sep 2026 – Present
• VLSI / Physical Design Internship
  Synopsys
  Jun 2026 – Present

Education

• B.Tech
  D Y Patil International University (DYPIU)
  Semiconductor Engineering · Aug 2025 – May 2028
• Diploma
  B Y Patil Polytechnic
  Electronics & Telecommunication Engineering · Jul 2022 – May 2025

Skills

• Python <3 months
• Verilog <3 months
• SystemVerilog <3 months
• TCL <3 months
• floor planning <3 months
• Routing <3 months
• Compiler design <3 months
• Placement <3 months
• Synopsys ICC2 <3 months

Tools / apps / platforms

• Linux <3 months
• UNIX <3 months

Projects

• 4-Bit ALU
  Verilog, VCS, Verdi, DC, ICC2

  Designed a 4-bit ALU with arithmetic and logical operations. Created a Verilog testbench and verified using VCS/Verdi. Practiced synthesis and physical-design implementation using ICC2.

• 4-Bit Up/Down Counter
  Verilog, VCS, Verdi, DC, ICC2

  Designed and verified a 4-bit up/down counter. Performed synthesis and physical design using DC and ICC2, including floorplanning, power planning, placement, CTS, routing, timing/area analysis, and GDSII generation.

Courses & certifications

• 5-Day Synopsys Physical Design Workshop · DYPIU · 2026
• 1-Month Synopsys VLSI / Physical Design Internship · Synopsys · 2026

🎯 Hobbies & interests

• Kabbadi