Rishikiran P

About

Electronics and Communication Engineering student with foundational knowledge in digital design and VLSI concepts. Interested in RTL design, digital verification, FPGA implementation, and chip architecture, with a goal of building a career in semiconductor design.

Education

• 2027 II
  B.Tech

  IIITDM Kurnool

  Electronics and Communication Engineering (ECE) · 2023 – 2027

  Electronics and Communication Engineering (ECE) · 2023 – 2027

Skills

Tools / apps / platforms

Languages

Projects

• Cache Memory Design
  Verilog

  Designed and implemented a basic cache memory architecture using Verilog. Explored cache optimization concepts including memory hierarchy and access patterns.

• Water Boat Prototype

  Designed and developed an autonomous water-based prototype combining electronics and mechanical systems. Integrated embedded systems and sensor-based control mechanisms.

• Smart Stick for Blind People

  Developed an assistive technology device combining sensors and embedded systems. Implemented obstacle detection and alert mechanisms.

• Metal Detector Device

  Designed a functional metal detection system using analog and digital circuits. Integrated circuit principles with practical hardware implementation.

• Cache Memory Design
  Verilog

  Designed and implemented a basic cache memory architecture using Verilog. Explored cache optimization concepts including memory hierarchy and access patterns.

• Water Boat Prototype

  Designed and developed an autonomous water-based prototype combining electronics and mechanical systems. Integrated embedded systems and sensor-based control mechanisms.

• Smart Stick for Blind People

  Developed an assistive technology device combining sensors and embedded systems. Implemented obstacle detection and alert mechanisms.

• Metal Detector Device

  Designed a functional metal detection system using analog and digital circuits. Integrated circuit principles with practical hardware implementation.

• Cache Memory Design
  Verilog

  Designed and implemented a basic cache memory architecture using Verilog. Explored cache optimization concepts including memory hierarchy and access patterns.

• Water Boat Prototype

  Designed and developed an autonomous water-based prototype combining electronics and mechanical systems. Integrated embedded systems and sensor-based control mechanisms.

• Smart Stick for Blind People

  Developed an assistive technology device combining sensors and embedded systems. Implemented obstacle detection and alert mechanisms.

• Metal Detector Device

  Designed a functional metal detection system using analog and digital circuits. Integrated circuit principles with practical hardware implementation.

• Cache Memory Design
  Verilog

  Designed and implemented a basic cache memory architecture using Verilog. Explored cache optimization concepts including memory hierarchy and access patterns.

• Water Boat Prototype

  Designed and developed an autonomous water-based prototype combining electronics and mechanical systems. Integrated embedded systems and sensor-based control mechanisms.

• Smart Stick for Blind People

  Developed an assistive technology device combining sensors and embedded systems. Implemented obstacle detection and alert mechanisms.

• Metal Detector Device

  Designed a functional metal detection system using analog and digital circuits. Integrated circuit principles with practical hardware implementation.

⚽ Extracurricular activities

• Class Representative

  Represented 60+ students and coordinated with faculty for academic and administrative matters. Facilitated communication between the student body and institute administration and organized class activities.

• Volleyball Team Captain

  Led and managed team performance in inter-college tournaments. Mentored junior players and fostered team cohesion and discipline.

🎯 Hobbies & interests

• Reading
• Technology
• Innovation