Rahul Walia

About

Ph.D. research scholar in Microelectronics and VLSI with experience in low-power VLSI, CMOS analog/mixed-signal IC design, frequency synthesis, and power management circuits. Works on PRBS generator ICs, LDO regulators, and post-layout verification using industry-standard EDA flows.

Experience

• Senior Research Fellow
  Indian Institute of Technology Ropar · Punjab, India
  Jul 2023 – Present

  Working on low-power programmable multiple uncorrelated output PRBS Generator ICs for high-speed communication and testing applications. Designed and tape-out verified a CMOS Low Dropout (LDO) Voltage Regulator in TSMC 65nm technology. Designed, fabricated, and tested a programmable PRBS Generator in SCL 180nm CMOS technology. Performed schematic design, simulation, verification, and post-layout analysis using Cadence Virtuoso and Calibre tools. Worked on low-power digital architectures, mixed-signal circuit design, and frequency synthesis techniques.

• Trainee
  CSIR-CSIO · Chandigarh, India
  Oct 2021 – Nov 2022

  Worked on a parallel signal detector approach for human activity detection using multiple seismic sensors. Implemented signal processing algorithms for activity recognition and detection applications. Research supported under CSIR-CSIO In-house Project Grant OLP246.

• Lecturer
  Global Research Institute of Management and Technology · Yamunanagar, India
  Dec 2017 – Nov 2020

  Taught Power Systems, Network Analysis and Synthesis, and Basic Electronics Engineering courses. Conducted laboratory sessions and guided undergraduate students in circuit analysis and simulation.

Education

• 2022 NI
  M.Tech

  NITTTR Chandigarh

  2020 – 2022

  2020 – 2022
• 2016 KU
  B.Tech

  Kurukshetra University

  2013 – 2016

  2013 – 2016
• 2023
  Ph.D. in Microelectronics and VLSI

  Indian Institute of Technology Ropar

  Microelectronics and VLSI · 2023

  Microelectronics and VLSI

Skills

Tools / apps / platforms

Projects

• Human Activity Detection Using Seismic Sensors
  single board computer

  Developed a multi-sensor seismic signal detection framework for identifying human activities. Applied parallel signal detection techniques for improved activity detection accuracy.

• Low Dropout (LDO) Voltage Regulator
  TSMC 65nm

  Designed a low-power CMOS LDO regulator in TSMC 65nm technology for on-chip voltage regulation applications. Performed transient, stability, line regulation, and load regulation analysis. Completed post-layout verification and successful tape-out of the design.

• Programmable PRBS Generator IC
  SCL 180nm CMOS

  Designed programmable PRBS architectures supporting PRBS7, PRBS15, PRBS23, and PRBS31 sequence generation. Integrated adaptive VDD control logic for low-power and configurable operation. Implemented and successfully tape-out verified the design in SCL 180nm CMOS technology. Performed post-silicon functional testing and validation of fabricated IC.

🏆 Achievements & awards

• Invited to Semicon India as a Core IC Designer of C2S0050

  Invited by Shri Ashwini Vaishnaw, Hon’ble Union Minister for Electronics and Information Technology, Government of India.

• Received fabricated IC chip C2S0081

  Received fabricated IC chip from Semiconductor Laboratory (SCL), Chandigarh, presented by Shri Ashwini Vaishnaw, as part of core IC design contributions.

• Completed CMOS IC tape-out in TSMC 65nm and SCL 180nm technologies

  Successfully completed tape-out work across two CMOS technology nodes.

📚 Publications

• High-performance paper-based DNA-conjugated Ti3 C2 Tx bionanoelectrode for rapid point-of-care detection of HPV-16 · 2025
• A Linearity Improved Equalizers for Short-Channel Communication Links · 2024
• A Resistorless Active Inductor Based CTLE · 2025
• A parallel signal detector approach for detection of human activities using multiple seismic sensors · 2024