Rachit Shukla

B.Tech student in Electronics and Communication Engineering

Kanpur, Uttar Pradesh, India

@rachit_shukla

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🎓 B.Tech in Electronics and Communication Engineering at Indian Institute of Information Technology, Ranchi · Graduating 2028

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About

Electronics and Communication Engineering student at Indian Institute of Information Technology Ranchi with hands-on experience in digital design, simulation, and Python-based application development. Builds RTL and software projects using Verilog/SystemVerilog, Python, and related tools.

Education

B.Tech

Indian Institute of Information Technology Ranchi

Electronics and Communication Engineering · 2024 – 2028
Senior Secondary Education

2024
Secondary Education

2022

Skills

<3 months

C UART Fsms NumPy Python Verilog Tkinter Matplotlib RTL Design Logic Design SystemVerilog Digital Design

Tools / apps / platforms

<3 months

Git VS Code

Projects

EchoCatch – Audio Recording & Playback Application

Python, Tkinter, sounddevice, NumPy, Matplotlib

Built a Python application for audio recording, playback, and waveform visualization with an interactive Tkinter interface. Used sounddevice for audio input/output and Python visualization tools to represent recorded signals. Applied signal-processing concepts to analyze and visualize recorded audio data.
Logic Gate Simulator

Python, Tkinter, Verilog

Developed a graphical logic-gate simulation application using Python and Tkinter for interactive digital-logic visualization. Implemented digital logic operations and translated hardware-design concepts into executable simulations. Integrated Verilog-based logic concepts to reinforce understanding of RTL and hardware design.
Verilog/SystemVerilog Digital Design

Verilog, SystemVerilog, Icarus Verilog, EDA Playground

Designed and simulated fundamental digital systems including MUX, Decoder, Encoder, Adders, Counters, FSMs, ALU, and UART using RTL methodologies. Developed testbenches and analyzed simulation waveforms to validate functional correctness of hardware designs. Applied structured RTL design practices across combinational and sequential logic blocks using Verilog/SystemVerilog.

Courses & certifications

Python with NumPy & Matplotlib · DataCode with Sharad
Python Developer · Mimo
System Design with Verilog · NPTEL

🏆 Achievements & awards

Silver Medal · 2018

Bharat Vikas Parishad Competition, Level 2

🤝 Volunteering

house of geeks · coordinator · 1989

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