Nimisha Borah

Nimisha Borah

B.Tech ECE student · Research Intern in VLSI, ML, and Solar Cells

Guwahati, Assam, India

@nimisha_borah

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Looking for jobs Looking for internships

About

Electronics and Communication undergraduate with research internship experience in perovskite solar cells, computer vision, and digital design. Interested in RTL design, functional verification, and deep learning-based robotics and vision systems.

Experience

  • Summer Research Intern
    IIT Guwahati
    Jun 2025 – 2025

    Simulated and optimized 2D/3D perovskite solar cells using SCAPS-1D, modeling absorber thickness, defect density, carrier transport layers, and temperature effects on performance. Designed a hierarchical bilayer of Cs2GeI2Br2 (2D) and Cs0.07FA0.85MA0.08Pb(IBr)3 (3D) to enhance light absorption and carrier extraction.

  • Winter Research Intern
    IIT Guwahati
    Dec 2024 – 2024

    Researched deep learning architectures including Transformer Networks, U-Net, CNN, and FastViT for computer vision tasks. Built a 3D hand mesh reconstruction model from 2D images using the FreiHAND dataset and trained and optimized models end-to-end using PyTorch and TensorFlow.

  • Summer Intern
    NIELIT
    Jul 2023 – 2023

    Designed a Low Pass FIR Filter in VHDL for ECG signal denoising. Worked on FPGA programming and Verilog-based digital circuit design with logic verification. Gained hands-on exposure to CAD tools for CMOS and NMOS gate-level development.

Education

Skills

6 to 12 months 6 to 12 months Most of a year behind them.
<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.

Tools / apps / platforms

<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
Proteus The MathWorks MATLAB

Projects

  • RTL Design and Functional Verification of an 8-Bit ALU
    Verilog HDL, Icarus Verilog, GTKWave

    Designed a synthesizable 8-bit ALU using Verilog HDL, developed testbenches, performed functional verification, and analysed simulation waveforms to debug logic errors and improve reliability.

  • RTL Synthesis and PPA Analysis of Digital Circuits
    Verilog, Yosys, OpenSTA

    Synthesized Verilog RTL designs into gate-level netlists, analysed timing reports and critical paths, and compared reports to evaluate Power, Performance, and Area trade-offs.

  • Proximal Policy Optimization (PPO)-Based Snake Robot Navigation using Reinforcement Learning
    PyBullet, Gymnasium, Stable-Baselines3, PPO

    Developed a PPO-based snake robot for autonomous navigation across multiple terrains and implemented curriculum learning to improve adaptability and locomotion.

📚 Publications

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