Mehul Jhunjhunwala

About

B.E. Electronics and Communication Engineering student with hands-on experience in RTL design, verification, analog fundamentals, and hardware testing. Interested in entry-level opportunities in VLSI and semiconductor roles, with exposure to industry-standard EDA tools and system-level debugging.

Experience

• Testing & Validation Engineer Intern
  SUN Mobility Pvt. Ltd. · Bengaluru, India
  Aug 2026 – Present

  Performed functional testing and validation of BMS PCBs against defined requirements. Verified voltage/current signals, protection functions, control responses, and communication interfaces. Executed test cases, analyzed results, and identified abnormal behavior and failures. Supported debugging, troubleshooting, and root-cause analysis of BMS hardware issues. Documented test results, failure logs, and validation reports.

• VLSI Training
  SureProTrust Ed
  Feb 2026 – Aug 2026

  Completed structured training covering MOS device physics and basic transistor-level working principles. Practiced RTL coding in Verilog and SystemVerilog, including simulation using Xilinx Vivado and Cadence Genus. Learned Design for Testability (DFT) concepts and their role in the RTL-to-silicon flow. Gained exposure to analog design fundamentals alongside digital RTL methodology.

• Technical Lead
  Deccterous
  Oct 2024 – Jul 2025

  Led a team of peers in end-to-end project development, providing hands-on technical mentorship and structured problem-solving guidance. Cultivated a collaborative culture that improved team throughput and deepened collective understanding of hardware design workflows.

Education

• 2026 NI
  B.E.

  National Institute of Engineering, Mysuru

  Awarded by VTU

  Electronics and Communication Engineering (ECE) · Nov 2022 – Jul 2026

  Electronics and Communication Engineering (ECE) · Nov 2022 – Jul 2026
• 2021 AB
  Senior Secondary

  Agrasain Boys' School

  May 2019 – Mar 2021

  May 2019 – Mar 2021
• 2019 AB
  High School

  Agrasain Boys' School

  Computer Science · May 2018 – Mar 2019

  Computer Science · May 2018 – Mar 2019

Skills

Tools / apps / platforms

Projects

• 4-bit Digital Ramp Analog-to-Digital Converter (ADC)

  Designed and tested a 4-bit counter-ramp ADC that converts sampled analog voltage levels into binary digital outputs. Gained insight into comparator-based threshold detection, timing constraints, and conversion trade-offs.

• 32×32-bit Synchronous FIFO
  Verilog

  Implemented a parameterised 32-deep, 32-bit-wide synchronous FIFO in Verilog with binary read/write pointer management, full/empty status flag generation, and an integrated RAM array.

• 4:1 Multiplexer Using Transmission Gate 2:1 MUX
  Cadence Virtuoso

  Designed a full-custom 4:1 multiplexer by cascading CMOS transmission gate-based 2:1 MUX cells in Cadence Virtuoso. Verified switching behaviour through transient simulations across process corners and confirmed layout integrity via DRC and LVS sign-off.

• Ultra-High-Speed PLL Design for 6G Communication
  45 nm CMOS

  Researched and evaluated PFD, Charge Pump, VCO, and Frequency Divider architectures optimized for high-frequency 6G applications. Explored low-jitter, high-speed topologies in 45 nm CMOS with a focus on minimizing phase noise and power consumption.

• Vending Machine Controller
  Verilog HDL, APB

  Architected a fully functional hardware vending machine controller using Verilog HDL. Implemented an FSM-based control engine with an APB configuration interface, on-chip memory management, multi-denomination currency handling, and automatic change return logic.

• 4-bit Digital Ramp Analog-to-Digital Converter (ADC)

  Designed and tested a 4-bit counter-ramp ADC that converts sampled analog voltage levels into binary digital outputs. Gained insight into comparator-based threshold detection, timing constraints, and conversion trade-offs.

• 32×32-bit Synchronous FIFO
  Verilog

  Implemented a parameterised 32-deep, 32-bit-wide synchronous FIFO in Verilog with binary read/write pointer management, full/empty status flag generation, and an integrated RAM array.

• 4:1 Multiplexer Using Transmission Gate 2:1 MUX
  Cadence Virtuoso

  Designed a full-custom 4:1 multiplexer by cascading CMOS transmission gate-based 2:1 MUX cells in Cadence Virtuoso. Verified switching behaviour through transient simulations across process corners and confirmed layout integrity via DRC and LVS sign-off.

• Ultra-High-Speed PLL Design for 6G Communication
  45 nm CMOS

  Researched and evaluated PFD, Charge Pump, VCO, and Frequency Divider architectures optimized for high-frequency 6G applications. Explored low-jitter, high-speed topologies in 45 nm CMOS with a focus on minimizing phase noise and power consumption.

• Vending Machine Controller
  Verilog HDL, APB

  Architected a fully functional hardware vending machine controller using Verilog HDL. Implemented an FSM-based control engine with an APB configuration interface, on-chip memory management, multi-denomination currency handling, and automatic change return logic.

Courses & certifications

• Arduino Platform C Programming · University of California, Irvine (Coursera)
• Microcontroller and Industrial Applications · L&T EduTech (Coursera)
• Digital Systems: From Logic Gates to Processors · Universitat Autònoma de Barcelona (Coursera)
• Arduino Platform C Programming · University of California, Irvine (Coursera)
• Microcontroller and Industrial Applications · L&T EduTech (Coursera)
• Digital Systems: From Logic Gates to Processors · Universitat Autònoma de Barcelona (Coursera)

⚽ Extracurricular activities

• Participation in VAIDYUTHAK State-Level Technical Event

  Participant in a state-level technical event organized by the NIE ECE Department.