Kaushik Reddy S

About

ASIC design verification candidate with hands-on experience in Verilog, SystemVerilog, UVM, self-checking testbenches, coverage closure, and protocol verification for AMBA and Ethernet MAC modules. Focused on building reusable verification components and improving functional and code coverage.

Education

• 2026 RV
  Advanced Diploma in ASIC Design

  RV-VLSI Design Center

  ASIC Design · 2026

  ASIC Design
• 2025 AI
  Bachelor of Engineering

  Dr Ambedkar Institute of Technology

  Electronics and Communication Engineering (ECE) · 2025

  Electronics and Communication Engineering (ECE)
• 2021 CP
  PUC

  Sri Chaitanya PU College

  2021
• 2019 CT
  SSLC

  Sri Chaitanya Techno School

  2019

Skills

Projects

• Verification of AMBA AHB Protocol using System Verilog
  SystemVerilog, Synopsys VCS

  Implemented the complete testbench architecture in SystemVerilog to verify bus communication protocol functionality, using OOP concepts for code reusability.

• Verification of AMBA APB Protocol using UVM
  UVM, Synopsys VCS

  Verified using UVM environment by developing sequences, assertions, and coverage for APB state transitions, improving functional coverage from 86.6% to 94% and achieving 95.5% code coverage, including corner cases for IDLE → SETUP → ACCESS.

• Verification of ETHERNET 10GE using UVM
  UVM, Synopsys VCS

  Verified Ethernet 10GE MAC TX/RX using UVM by developing bring-up, oversized, and missing SOP/EOP testcases, implementing driver, monitor, and sequences to ensure data integrity and TX-RX synchronization, achieving 83.33% functional and code coverage.