About
B.Tech student in Electronics and Communication Engineering with a focus on ASIC design, low-power VLSI, Verilog, RTL design, and UPF-based power management. Interested in applying hands-on semiconductor design skills to real-world power-efficient design challenges.
Experience
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InternDefence Research and Development Organisation (DRDO), Centre for Advanced Systems (CAS)Aug 2026 – Present
Education
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B.Tech in Electronics and Communication EngineeringElectronics and Communication Engineering · Aug 2023 – May 2027
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Intermediate (MPC)Dr. Himasekhar Junior CollegeMPC · 2023 – 2023
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Secondary School Certificate (SSC)Bhashyam Educational Institutions2021 – 2021
Skills
Tools / apps / platforms
Projects
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EchoBridge – Smart Audio Awareness System
Developing a smart audio awareness system that alerts users when someone calls them while using earphones, with customizable voice-trigger detection and smartphone/smartwatch connectivity.
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Smart Sensor Hub – UPF Power Domain DesignVerilog HDL, UPF (IEEE 1801), Synopsys Design Compiler (DC Shell)
Designed a low-power VLSI system with four power domains, implemented power gating, isolation cells, level shifters, and retention registers across ON, SLEEP, and DEEP SLEEP states.
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Dual-Window Watchdog Timer – Multi-Domain UPF Power Intent DesignVerilog HDL, Icarus Verilog, GTKWave, Yosys, Synopsys Design Compiler, UPF
Designed and verified a Dual-Window Watchdog Timer for fault detection and system monitoring. Developed RTL modules, performed RTL simulation, and explored UPF-based low-power design and synthesis flow.
🏆 Achievements & awards
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ISWDP Samsung Fellowship · 2025
Recipient for academic excellence, technical aptitude, and potential in semiconductor and VLSI research.
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IEEE Electronic Devices Society (EDS) Membership · 2025
Professional member demonstrating active interest in electronic devices, semiconductor technology, and VLSI innovation.