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JR

Jagadheeswaran R

VLSI / RTL Design & Verification Engineer

Bangalore, Karnataka, India

@jagadheeswaran_r

0 followers

🎓 PG Diploma in Advanced VLSI at IIIT Bangalore · Graduating 2026

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About

Electronics and Communication Engineering graduate with hands-on experience in RTL design, verification, and embedded/IoT projects. Good working understanding of SystemVerilog, UVM, CMOS, synthesis, STA, and ASIC flow.

Education

  • PG Diploma in Advanced VLSI
    IIIT Bangalore
    Mar 2026 – Sep 2026
  • Bachelor of Engineering
    Nitte Meenakshi Institute of Technology
    Awarded by nitte
    Electronics and Communication Engineering (ECE) · 2020 – Jun 2024

Skills

<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
C UVM VHDL CMOS Verilog Xilinx Ise SystemVerilog Shell Scripting HCM Data Loader (HDL) Synthesis (Synplicity)

Tools / apps / platforms

<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
Linux Arduino Microsoft Windows The MathWorks MATLAB

Languages

Native / Bilingual Native / Bilingual Their first language, or as strong as one.
Tamil Speak English Speak

Projects

  • UV Photodetector for Sensing Applications
    Semiconductor Fabrication, Material Engineering

    Developed a UV photodetector using advanced semiconductor materials for high sensitivity and fast response.

  • Supercapacitor for Energy Storage
    Electrochemical Analysis, Material Science Techniques

    Designed and developed a supercapacitor system focused on improved energy storage efficiency and charge-discharge cycles.

  • SSB and VSB Modulation & Demodulation Systems
    MATLAB/Simulink, Analog Communication Circuits

    Designed and analyzed modulation and demodulation systems to improve signal transmission efficiency and bandwidth utilization.

  • Analysis of Energy Harvesting using IoT Networks
    ESP32/Arduino, IoT Sensors, Thing Speak/Blynk, Embedded C

    Designed and implemented an IoT-based energy harvesting system for monitoring and optimizing renewable energy usage.

  • Router 1x3 – RTL Design and Verification
    Verilog, SystemVerilog, UVM, Xilinx ISE-14.5, Riviera-PRO

    Designed, implemented, synthesized and verified a 1x3 router that routes 8-bit packets to three output channels.

Courses & certifications

  • PG Diploma in Advanced VLSI · FutureWiz Academy · 2026

🏆 Achievements & awards

  • Appreciation Award

    Received appreciation for great working commitment during expo.

🎯 Hobbies & interests

  • Reading Books
  • Internet Surfing

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