HK

Harshitha Keshav

ECE graduate · Embedded Systems, RTL Design & Verification

Bengaluru, Karnataka, India

@harshitha_keshav

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Looking for jobs Looking for internships Open to relocating

About

ECE graduate with practical experience in Embedded Systems, RTL Design, and Functional Verification. Skilled in Verilog HDL, SystemVerilog, ESP32, LoRa, and digital electronics, with project experience in communication systems and protocol design.

Education

  • B.E. Electronics & Communication Engineering
    SJBIT
    Electronics & Communication Engineering · 2022 – 2026
  • PUC
    The National PU College
    PCMC · 2020 – 2022
  • SSLC
    Vijaya High School
    2019 – 2020

Skills

  • C <3 months
  • Python <3 months
  • Digital Electronics <3 months
  • ESP32 <3 months
  • UART <3 months
  • SystemVerilog <3 months
  • Sensor Integration <3 months
  • Testing and Validation <3 months
  • Hardware Prototyping <3 months
  • Functional Verification <3 months
  • FIFO <3 months
  • Testbench Development <3 months
  • RTL Design <3 months
  • Fsms <3 months
  • Verilog Hdl <3 months
  • LoRA <3 months
  • GPS (RTK) <3 months

Tools / apps / platforms

  • Arduino IDE <3 months

Projects

  • ESP8266, LoRa, GPS, Wi-Fi, web interface

    Designed an ESP8266-based LoRa communication network for long-range emergency messaging with minimal power consumption. Implemented solar-powered energy harvesting and battery management, and integrated GPS, Wi-Fi, and web monitoring for SOS messaging and location tracking.

  • UART Protocol Design & Implementation
    Verilog HDL

    Ongoing project designing and implementing UART transmitter and receiver modules with configurable baud rate generation, data transmission/reception, and simulation-based verification.

  • Synchronous FIFO Design using Verilog HDL
    Verilog HDL

    Designed and implemented a synchronous FIFO digital buffering system, developed test cases, and performed simulation-based testing and debugging.

Courses & certifications

  • KVLSI Cohort 3 · IIIT Bangalore · 2026
  • System Design Using Verilog · NPTEL

🏆 Achievements & awards

  • Published Research Paper · 2025

    Solar-Powered LoRa Mesh Network for Emergency Communication and Tracking During Disasters (IJARCCE)

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