Durga S

About

Electronics and Communication Engineering graduate focused on RTL design, design verification, and FPGA-based digital system development. Has hands-on experience with Verilog, AXI4-Stream, self-checking testbenches, Vivado, and semiconductor design, and has published IEEE research.

Experience

• VLSI Design for Testability (DFT) Intern
  BIST Technologies Pvt. Ltd.
  Dec 2024 – Apr 2025

  Developed CMOS digital circuits including inverter, NAND, NOR, and half adder using Cadence Virtuoso and Microwind. Performed DRC and LVS verification and gained exposure to scan chain insertion, ATPG flow, stuck-at fault models, and DFT methodologies.

Education

• B.Tech
  Velagapudi Ramakrishna Siddhartha Engineering College
  Electronics and Communication Engineering · 2022 – 2026

Skills

• C <3 months
• Python <3 months
• Digital Design <3 months
• Verilog <3 months
• Functional Verification <3 months
• Testbench Development <3 months
• RTL Design <3 months
• Axi4-Stream <3 months
• FPGA Design <3 months

Tools / apps / platforms

• Cadence Virtuoso Layout Suite <3 months

Languages

• English Conversational Speak · Read · Write
• Telugu Native / Bilingual Speak · Read · Write

Projects

• FPGA Digital Design Implementation
  Verilog, Xilinx Vivado

  Implemented Verilog-based digital designs on the Nexys 4 DDR FPGA and verified functionality using the Vivado design flow.

• Compact SRAM Decoder Optimization
  Cadence Virtuoso

  Designed and simulated 2x2 and 4x4 SRAM decoder circuits and analyzed power and delay characteristics.

• AXI4-Stream Data Width Converter
  Verilog RTL, Xilinx Vivado

  Developed a configurable AXI4-Stream downsizer in synthesizable Verilog supporting multiple data-width conversions. Built a self-checking testbench, performed behavioral simulation and functional verification, and packaged the design as reusable custom IP.

Courses & certifications

• CCNA: Switching, Routing, and Wireless Essentials · Cisco Networking Academy · 2026
• VLSI Design Training · SkillDzire · 2026
• VLSI Design for Testability (DFT) · BIST Technologies · 2025

🏆 Achievements & awards

• All India Rank 48 in Naukri Campus Aptitude Test (NCAT)

  Secured rank 48 among 4.5 lakh+ participants nationwide.

📚 Publications

• Efficient Data Width Conversion using AXI Stream Downsizer in Verilog · 2025
• Stability and Delay Trade-offs in 6T SRAM Cell at 45 nm and 90 nm · 2025

🎯 Hobbies & interests

• Podcasts and sketching