Anurag Chauhan

VLSI Design & Verification Engineer

Ghaziabad, Uttar Pradesh, India

@anurag_chauhan

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About

Electronics & Communication Engineering graduate who completed PGCP in VLSI Design at C-DAC Noida in August 2026 with hands-on experience in Verilog RTL Design, SystemVerilog/UVM verification, AXI4-Lite protocol verification, assertions, functional coverage, constrained random verification, and scoreboarding. Seeking Front-End RTL Design and Design Verification opportunities.

Experience

Automation Engineer

LETUS Automation Pvt. Ltd.

May 2024 – Oct 2025

Interpreted VFD technical datasheets, performed wiring and validation of AC drives, configured VFD parameter groups, executed functional verification and debugging of refurbished drives, maintained verification reports and technical documentation, and collaborated with vendors and refurbishment teams.

Education

Post Graduate Certificate Program (PGCP) in VLSI Design

C-DAC Noida

VLSI Design · 2026 – 2026
Bachelor of Technology (B.Tech.)

ABES Engineering College

Electronics and Communication Engineering (ECE) · 2019 – 2023
Class XII

Ryan International School, Ghaziabad

Science · 2018 – 2019
Class X

Ryan International School, Ghaziabad

2017 – 2018

Skills

1 to 2 years

Debugging

<3 months

C I2C TCL SPI UVM UART Fsms Python Verilog RTL Design SystemVerilog CMOS Technology Digital Electronics System Architecture Functional Coverage Coverage-driven verification Constrained Random Verification

Tools / apps / platforms

<3 months

Linux Claude AI Midjourney Google Gemini OpenAI ChatGPT Microsoft Copilot Synopsys Design Compiler

Projects

AXI4-Lite Watchdog Timer Design & Verification

Verilog, SystemVerilog

Designed and verified a synthesizable AXI4-Lite watchdog timer slave with register interface, timeout detection, reset generation, and constrained-random verification.
Parameterized 2D Systolic Array AI Matrix Multiplication Accelerator

Verilog, SystemVerilog, UVM

Designed a parameterized NxN systolic array RTL architecture and built directed and UVM-based verification environments with assertions, functional coverage, constrained-random testing, and scoreboarding.

🏆 Achievements & awards

AIR 1 · 2026

C-DAC PGCP-VLSI, February 2026 Batch
AIR 7 · 2026

C-CAT Examination, January 2026
First Division with Distinction · 2023

Graduated B.Tech. with 81%

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