MUTCHAKARLA ANITHA

About

Electronics and Communication Engineering graduate with hands-on experience in VLSI design, digital logic, and embedded systems through academic projects and internships. Has worked with Verilog HDL, FPGA implementation, and RTL design, and is seeking an entry-level opportunity in VLSI and embedded systems.

Experience

• VLSI Design Internship
  Excelr

  Completed a 4-month internship focused on VLSI design concepts, RTL design, and simulation using Verilog HDL.

• VLSI Design Internship

  Completed a 6-week internship gaining practical exposure to VLSI design flow and hands-on project implementation.

• IoT Internship

  Gained hands-on exposure to sensors, communication protocols, and fundamentals of embedded system.

Education

• 2026 GV
  B.Tech

  Gayatri Vidya Parishad College of Engineering for Women

  Electronics and Communication Engineering (ECE) · 2022 – 2026

  Electronics and Communication Engineering (ECE) · 2022 – 2026
• 2022 AP
  Intermediate (MPC)

  AP Model College

  2020 – 2022

  2020 – 2022
• 2020 AP
  SSC

  AP Model School

  2020 – 2020

  2020 – 2020

Skills

Projects

• IoT-Based Smart Security System

  Developed a smart security system integrating sensors and real-time monitoring for security applications. Implemented remote access and control through a mobile application with automated alerts.

• Watchdog Timer using Verilog HDL

  Designed and implemented a Watchdog Timer using Verilog HDL for system monitoring and recovery from abnormal operating conditions. Developed and verified the RTL design through simulation.

• Design of High-Speed Counters and Performance Evaluation in ADPLL
  Verilog HDL, Xilinx ISE, Spartan-6 FPGA

  Designed and implemented high-speed synchronous counter architectures, including binary and Johnson counters, using Verilog HDL. Synthesized and evaluated the counter architectures using Xilinx ISE, comparing timing performance and maximum operating frequency for different counter widths. Designed the ADPLL architecture in Verilog HDL, integrating high-speed counters into the feedback divider and DCO architecture. Evaluated the effect of different counter architectures on ADPLL operating frequency and locking performance through simulation and synthesis. Implemented and validated the optimized ADPLL architecture on a Spartan-6 FPGA through hardware testing.